1. Field of the Invention
The specification, the drawings, and the scope of claims of the present application (hereinafter referred to as “this specification and the like”) disclose a memory circuit, a logic circuit, a processing device, other semiconductor devices, a driving method thereof, a manufacturing method thereof, and the like. The technical field of one embodiment of the present invention is not limited thereto. For example, one embodiment of the present invention relates to a semiconductor device, a memory device, a processing device, an imaging device, a display device, a light-emitting device, a storage device, a driving method thereof, or a manufacturing method thereof.
2. Description of the Related Art
As memory cells used in random access memories (RAMs), 1T1C (one transistor-one capacitor)-type memory cells and 2T-type or 3T-type gain cells are known. Moreover, it has been proposed that a transistor whose channel in an active layer is formed of an oxide semiconductor (hereinafter also referred to as “an oxide semiconductor transistor” or “an OS transistor”) is employed as a writing transistor in those memory cells.
For example, Patent Document 1 discloses a memory cell that can retain data even in the situation in which electric power is not supplied, by including the OS transistor as a writing transistor. For example, Patent Documents 2-4 disclose memory cells including an OS transistor and capable of multi-level data retention.
The microfabrication and storage of more levels of data of nonvolatile memory devices increase the possibility of errors. Therefore, an operation for detecting whether the retained data contains an error is performed. For example, in Patent Document 4, detection of an error is enabled by setting a memory cell to have more than 2X data levels and making the memory cell retain X-bit data and an error bit. In a reading operation, 2X levels of data are decoded and the confidence coefficient of the X-bit data is determined with the use of the error bit.